24 free digital logic tools. Simplify expressions, solve Karnaugh maps, export to Structured Text, Ladder Logic & VHDL.
Integrate Boolean simplification into your pipeline. REST API, JSON in/out.
POST https://n8n.iaspacdz.live/webhook/api/optimize Authorization: Bearer YOUR_API_KEY Content-Type: application/json
{
"expression": "A AND B OR A AND C OR NOT A AND B",
"output_format": "boolean"
}{
"truth_table": {
"variables": ["A", "B", "C"],
"outputs": [0, 0, 1, 1, 0, 1, 1, 1]
},
"output_format": "structured_text"
}{
"original": "A AND B OR A AND C OR NOT A AND B",
"simplified": "B OR (A AND C)",
"reduction_percent": 42,
"gates_original": 5,
"gates_simplified": 3,
"verified": true,
"structured_text": "output := B OR (A AND C);",
"ladder_logic": "--[B]----(OUT)--\n--[A]--[C]--(OUT)--",
"vhdl": "output <= B or (A and C);"
}// Available output_format values: "boolean" // Default "structured_text" // IEC 61131-3 "ladder" // Ladder Logic (ASCII) "vhdl" // VHDL signal assignment "all" // All formats
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Built for engineers, students, and developers.
Clean up legacy ladder logic. Reduce gate count in existing PLCs. Export directly to Structured Text for Siemens, Allen-Bradley, Schneider.
Solve Karnaugh maps instantly. Verify your Boolean algebra homework. Understand step-by-step simplification with truth tables.
Simplify complex IF/ELSE workflows. Turn messy conditional logic into clean, minimal expressions for Zapier, Make, n8n.
Optimize gate count for synthesis. Export to VHDL. Reduce LUT usage and improve timing closure on Xilinx, Intel, Lattice FPGAs.
Everything you need for digital logic, in one place.